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Электронный компонент: UC1825B

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FEATURES
Improved versions of the
UC3823/UC3825 PWMs
Compatible with Voltage or
Current-Mode Topologies
Practical Operation at Switching
Frequencies to 1MHz
50ns Propagation Delay to Output
High Current Dual Totem Pole
Outputs (2A Peak)
Trimmed Oscillator Discharge
Current
Low 100
A Startup Current
Pulse-by-Pulse Current Limiting
Comparator
Latched Overcurrent Comparator
With Full Cycle Restart
UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
High Speed PWM Controller
DESCRIPTION
The UC3823A & B and the UC3825A & B family of PWM control ICs are im-
proved versions of the standard UC3823 & UC3825 family. Performance en-
hancements have been made to several of the circuit blocks. Error amplifier gain
bandwidth product is 12MHz while input offset voltage is 2mV. Current limit
threshold is guaranteed to a tolerance of 5%. Oscillator discharge current is spec-
ified at 10mA for accurate dead time control. Frequency accuracy is improved
to 6%. Startup supply current, typically 100
A, is ideal for off-line applications.
The output drivers are redesigned to actively sink current during UVLO at no
expense to the startup current specification. In addition each output is capable
of 2A peak currents during transitions.
Functional improvements have also been implemented in this family. The
UC3825 shutdown comparator is now a high-speed overcurrent comparator with
a threshold of 1.2V. The overcurrent comparator sets a latch that ensures full
discharge of the soft start capacitor before allowing a restart. While the fault latch
is set, the outputs are in the low state. In the event of continuous faults, the soft
start capacitor is fully charged before discharge to insure that the fault frequency
does not exceed the designed soft start period. The UC3825 Clock pin has be-
come CLK/LEB. This pin combines the functions of clock output and leading
edge blanking adjustment and has been buffered for easier interfacing.
* Note: 1823A,B Version Toggles Q and Q are always low
9/95
BLOCK DIAGRAM
continued
UDG-95101
2
The UC3825A,B has dual alternating outputs and the same
pin configuration of the UC3825. The UC3823A,B outputs op-
erate in phase with duty cycles from zero to less than 100%.
The pin configuration of the UC3823A,B is the same as the
UC3823 except pin 11 is now an output pin instead of the ref-
erence pin to the current limit comparator. "A" version parts
have UVLO thresholds identical to the original UC3823/25.
The "B" versions have UVLO thresholds of 16 and 10V, in-
tended for ease of use in off-line applications.
Consult Application Note U-128 for detailed technical and ap-
plications information. Contact the factory for further pack-
aging and availability information.
UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
CONNECTION DIAGRAMS
Supply Voltage (VC, VCC) ....................................................22V
Output Current, Source or Sink (Pins OUTA, OUTB)
DC ..................................................................................0.5A
Pulse (0.5
s) ...................................................................2.2A
Power Ground (PGND) ......................................................
0.2V
Analog Inputs
(INV, NI, RAMP)...................................................
-
0.3V to 7V
(ILIM, SS).............................................................
-
0.3V to 6V
Clock Output Current (CLK/LEB) .......................................
-
5mA
Error Amplifier Output Current (EAOUT)..............................5mA
Soft Start Sink Current (SS) ...............................................20mA
Oscillator Charging Current (RT)........................................
-
5mA
Power Dissipation at T
A
=
60
C..............................................1W
Storage Temperature Range ............................
-
65
C to
+
150
C
Junction Temperature.......................................
-
55
C to
+
150
C
Lead Temperature (Soldering, 10 sec.) .............................300
C
All currents are positive into, negative out of the specified terminal.
Consult Packaging Section of Databook for thermal limitations
and considerations of packages.
DIL-16, SOIC-16, (Top View)
J or N Package; DW Package
PLCC-20, LCC-20, (Top View)
Q, L Packages
Device
UVLO
D
MAX
UC3823A
9.2V/8.4V
<
100%
UC3823B
16V/10V
<
100%
UC3825A
9.2V/8.4V
<
50%
UC3825B
16V/10V
<
50%
DESCRIPTION (cont.)
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply for T
A
=
-
55
C to
+
125
C for the
UC1823A,B and UC1825A,B;
-
40
C to
+
85
C for the UC2823A,B and UC2825A,B; 0
C to
+
70
C for the UC3823A,B and
UC3825A,B; RT
=
3.65k, CT
=
1nF, VCC
=
12V, T
A
=
T
J
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Reference Section
Output Voltage
T
J
=
25
C, Io
=
1mA
5.05
5.1
5.15
V
Line Regulation
12
<
VCC
<
20V
2
15
mV
Load Regulation
1mA
<
Io
<
10mA
5
20
mV
Total Output Variation
Line, Load, Temp
5.03
5.17
V
Temperature Stability
T
MIN
<
T
A
<
T
MAX
(Note 1)
0.2
0.4
mV/
C
Output Noise Voltage
10Hz
<
f
<
10kHz (Note 1)
50
VRMS
Long Term Stability
T
J
=
125
C, 1000 hours (Note 1)
5
25
mV
Short Circuit Current
VREF
=
0V
30
60
90
mA
3
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Oscillator Section
Initial Accuracy
T
J
=
25
C (Note 1)
375
400
425
kHz
Total Variation
Line, Temperature (Note 1)
350
450
kHz
Voltage Stability
12V
<
VCC
<
20V
1
%
Temperature Stability
T
MIN
<
T
A
<
T
MAX
(Note 1)
5
%
Initial Accuracy
RT
=
6.6k, CT
=
220pF T
A
=
25
C (Note 1)
0.9
1
1.1
MHz
Total Variation
RT
=
6.6k, CT
=
220pF (Note 1)
0.85
1.15
MHz
Clock Out High
3.7
4
V
Clock Out Low
0
0.2
V
Ramp Peak
2.6
2.8
3
V
Ramp Valley
0.7
1
1.25
V
Ramp Valley to Peak
1.6
1.8
2
V
Oscillator Discharge Current
RT
=
Open, V
CT
=
2V
9
10
11
mA
Error Amplifier Section
Input Offset Voltage
2
10
mV
Input Bias Current
0.6
3
A
Input Offset Current
0.1
1
A
Open Loop Gain
1V
<
Vo
<
4V
60
95
dB
CMRR
1.5V
<
V
CM
<
5.5V
75
95
dB
PSRR
12V
<
VCC
<
20V
85
110
dB
Output Sink Current
V
EAOUT
=
1V
1
2.5
mA
Output Source Current
V
EAOUT
=
4V
-
0.5
-
1.3
mA
Output High Voltage
I
EAOUT
= -
0.5mA
4.5
4.7
5
V
Output Low Voltage
I
EAOUT
=
1mA
0
0.5
1
V
Gain Bandwidth Product
F
=
200kHz
6
12
MHz
Slew Rate
(Note 1)
6
9
V/
s
PWM Comparator
RAMP Bias current
V
RAMP
=
0V
-
1
-
8
A
Minimum Duty Cycle
0
%
Maximum Duty Cycle
85
%
Leading Edge Blanking
R
=
2k, C
=
470pF
300
375
450
ns
LEB Resistor
V
CLK
/
LEB
=
3V
8.5
10
11.5
kohm
EAOUT Zero D.C. Threshold
V
RAMP
=
0V
1.1
1.25
1.4
V
Delay to Output
V
EAOUT
=
2.1V, V
RAMP
=
0 to 2V Step (Note 1)
50
80
ns
Current Limit/Start Sequence/Fault Section
Soft Start Charge Current
V
SS
=
2.5V
8
14
20
A
Full Soft Start Threshold
4.3
5
V
Restart Discharge Current
V
SS
=
2.5V
100
250
350
A
Restart Threshold
0.3
0.5
V
ILIM Bias Current
0
<
V
ILIM
<
2V
15
A
Current Limit Threshold
0.95
1
1.05
V
UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
ELECTRICAL CHARACTERISTICS (cont.)
Unless otherwise stated, these specifications apply for T
A
=
-
55
C to
+
125
C for the UC1823A,B and UC1825A,B;
-
40
C to
+
85
C for the UC2823A,B and UC2825A,B; 0
C to
+
70
C for the
UC3823A,B and UC3825A,B; RT
=
3.65k, CT
=
1nF, VCC
=
12V, T
A
=
T
J
.
4
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Current Limit/Start Sequence/Fault Section (cont.)
Over Current Threshold
1.14
1.2
1.26
V
ILIM Delay to Output
V
ILIM
=
0 to 2V Step (Note 1)
50
80
ns
Output Section
Output Low Saturation
I
OUT
=
20mA
0.25
0.4
V
I
OUT
= 200mA
1.2
2.2
V
Output High Saturation
I
OUT
=
20mA
1.9
2.9
V
I
OUT
= 200mA
2
3
V
UVLO Output Low Saturation
I
O
=
20mA
0.8
1.2
V
Rise/Fall Time
C
L
=
1nF (Note 1)
20
45
ns
UnderVoltage Lockout
Start Threshold
UCX823B and X825B only
16
17
V
Stop Threshold
UCX823B and X825B only
9
10
V
UVLO Hysteresis
UCX823B and X825B only
5
6
7
V
Start Threshold
UCX823A and X825A only
8.4
9.2
9.6
V
UVLO Hysteresis
UCX823A and X825A only
0.4
0.8
1.2
V
Supply Current
Startup Current
VC
=
VCC
=
V
TH
(start) - 0.5V
100
300
A
Icc
28
36
mA
UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
Note 1: Guaranteed by design. Not 100% tested in production.
ELECTRICAL CHARACTERISTICS (cont.)
Unless otherwise stated, these specifications apply for T
A
=
-
55
C to
+
125
C for the UC1823A,B and UC1825A,B;
-
40
C to
+
85
C for the UC2823A,B and UC2825A,B; 0
C to
+
70
C for the
UC3823A,B and UC3825A,B; RT
=
3.65k, CT
=
1nF, VCC
=
12V, T
A
=
T
J
.
OSCILLATOR
The UC3823A,B/3825A,B oscillator is a saw tooth. The
rising edge is governed by a current controlled by the RT
pin and value of capacitance at the CT pin. The falling
edge of the sawtooth sets dead time for the outputs. Se-
lection of RT should be done first, based on desired max-
imum duty cycle. CT can then be chosen based on de-
sired frequency, RT, and D
MAX
. The design equations
are:
RT =
CT =
Recommended values for RT range from 1k to 100k.
Control of D
MAX
less than 70% is not recommended.
(1.6 D
MAX
)
(RT F)
3V
(10mA) (1 - D
MAX
)
APPLICATIONS INFORMATION
Oscillator
UDG-95102
5
UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
APPLICATIONS INFORMATION (cont.)
Maximum Duty Cycle vs R
T
Curve
Oscillator Frequency vs. R
T
and C
T
Curve
OSCILLATOR (cont.)
LEADING EDGE BLANKING
The UC3823A,B/3825A,B performs fixed frequency pulse
width modulation control. The UC3823A,B outputs oper-
ate together at the switching frequency and can vary from
0 to some value less than 100%. The UC3825A,B outputs
are alternately controlled. During every other cycle, one
output will be off. Each output then, switches at one-half
the oscillator frequency, varying in duty cycle from 0 to less
than 50%.
To limit maximum duty cycle, the internal clock pulse
blanks both outputs low during the discharge time of the
oscillator. On the falling edge of the clock, the appropriate
output(s) is driven high. The end of the pulse is controlled
by the PWM comparator, current limit comparator, or the
overcurrent comparator.
Normally the PWM comparator will sense a ramp cross-
ing a control voltage (error amp output) and terminate the
pulse. Leading edge blanking (LEB) causes the PWM
comparator to be ignored for a fixed amount of time after
the start of the pulse. This allows noise inherent with
switched mode power conversion to be rejected. The
PWM ramp input may not require any filtering as result of
leading edge blanking.
To program a Leading Edge Blanking period, connect a
capacitor, C, to CLK/LEB. The discharge time set by C and
the internal 10k resistor will determine the blanked inter-
val. The 10k resistor has a 10% tolerance. For more ac-
curacy, an external 2k 1% resistor, R, can be added, re-
sulting in an equivalent resistance of 1.66k with a tolerance
of 2.4%. The design equation is:
t
LEB
= 0.5 (R | | 10k) C.
Values of R less than 2k should not be used
Leading edge blanking is also applied to the current limit
comparator. After LEB, if the ILIM pin exceeds the one
volt threshold, the pulse is terminated. The over current
comparator, however, is not blanked. It will catch catas-
trophic over current faults without a blanking delay. Any
time the ILIM pin exceeds 1.2V, the fault latch will be set
and the outputs driven low. For this reason, some noise
filtering may be required on the ILIM pin.
LEB Operational Waveforms
UDG-95103
UDG-95104
UDG-95105
6
UVLO, SOFT START AND FAULT MANAGEMENT
Soft start is programmed by a capacitor on the SS pin. At
power up, SS is discharged. When SS is low, the error amp
output is also forced low. As the internal 9
A source
charges the SS pin, the error amp output follows until
closed loop regulation takes over.
Anytime ILIM exceeds 1.2V, the fault latch will be set and
the output pins will be driven low. The soft start cap is then
discharged by a 250
A current sink. No more output
pulses are allowed until soft start is fully discharged, and
ILIM is below 1.2V. At this point the fault latch will be re-
set and the chip will execute a soft start.
Should the fault latch be set during soft start, the outputs
will be immediately terminated, but the soft start cap will
not be discharged until it has been fully charged. This re-
sults in a controlled hiccup interval for continuous fault con-
ditions.
UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
APPLICATIONS INFORMATION (cont.)
Soft Start and Fault Waveforms
UDG-95106
ACTIVE LOW OUTPUTS DURING UVLO
The UVLO function forces the outputs to be low and con-
siders both VCC and VREF before allowing the chip to
operate.
Output V and I During UVLO
Simplified Schematic
PWM APPLICATIONS
Current Mode
Voltage Mode
UDG-95107
UDG-95108
UDG-95109
UDG-95110
7
UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
SYNCHRONIZATION
The oscillator can be synchronized by an external pulse
inserted in series with the timing capacitor. Program the
free running frequency of the oscillator to be 10 to 15%
slower than the desired synchronous frequency. The
pulse width should be greater than 10ns and less than
half the discharge time of the oscillator. The rising edge
of the CLK/LEB pin can be used to generate a synchro-
nizing pulse for other chips. Note that, the CLK/LEB pin
will no longer accept an incoming synchronizing signal.
General Oscillator Synchronization
Operational Waveforms
Two Units
APPLICATIONS INFORMATION (cont.)
HIGH CURRENT OUTPUTS
Each totem pole output of the UC3823A,B and
UC3825A,B can deliver a 2 amp peak current into a ca-
pacitive load. The output can slew a 1000pF capacitor 15
volts in approximately 20 nanoseconds. Separate col-
lector supply (VC) and power ground (PGND) pins help
decouple the IC's analog circuitry from the high power
gate drive noise. The use of 3 Amp Schottky diodes
(1N5120, USD245 or equivalent) as shown in the figure
from each output to both VC and PGND are recom-
mended. The diodes clamp the output swing to the sup-
ply rails, necessary with any type of inductive/capacitive
load, typical of a MOSFET gate. Schottky diodes must
be used because a low forward voltage drop is required.
DO NOT USE standard silicon diodes.
Although a "single ended" device, two output drivers are
available on the UC3823A,B devices. These can be "par-
alleled" by the use of a one-half ohm (noninductive) re-
sistor connected in series with each output for a com-
bined peak current of 4 Amps.
Power MOSFET Drive Circuit
UDG-95111
UDG-95113
UDG-95112
UDG-95114
8
GROUND PLANES
Each output driver of these devices is capable of 2A peak
currents. Careful layout is essential for correct operation of
the chip. A ground plane must be employed. A unique sec-
tion of the ground plane must be designated for high di/dt
currents associated with the output stages. This point is the
power ground to which the PGND pin is connected. Power
ground can be separated from the rest of the ground plane
and connected at a single point, although this is not strictly
necessary if the high di/dt paths are well understood and
accounted for. VCC should be bypassed directly to power
ground with a good high frequency capacitor. The sources
UC1823A,B/1825A,B
UC2823A,B/2825A,B
UC3823A,B/3825A,B
of the power MOSFET should connect to power ground
as should the return connection for input power to the sys-
tem and the bulk input capacitor. The output should be
clamped with a high current Schottky diode to both VCC
and PGND. Nothing else should be connected to power
ground.
VREF should be bypassed directly to the signal portion
of the ground plane with a good high frequency capaci-
tor. Low ESR/ESL ceramic 1
F capacitors are recom-
mended for both VCC and VREF. All analog circuitry
should likewise be bypassed to the signal ground plane.
APPLICATIONS INFORMATION (cont.)
UDG-95115
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD.
MERRIMACK, NH 03054
TEL.(603) 424-2410
FAX (603) 424-3460
grounding and bypass procedures should be followed.
The use of a ground plane is highly recommended.
Open Loop Test Circuit
This test fixture is useful for exercising many of the
UC3823A,B, UC3825A,B functions and measuring their
specifications. As with any wideband circuit, careful
UDG-95116
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1999, Texas Instruments Incorporated